Nano-scale CMOS and Low Voltage Analog to Digital Converter Design Challenges

This paper discusses the analog performance trend and the performance estimation of pipeline ADC in nano-scale CMOS era. The technology scaling is effective to increase the conversion rate, however it is not effective to increase the resolution, SNR, and decrease the power consumption at higher resolution. New converter design challenge is needed and one strong candidate must be the successive approximation ADC because it does not require operational amplifiers that consume power and become difficult to design with nano-scale CMOS