Title :
An 1 V 6.25 GHz PLL with 0.5 ps rms Jitter in 0.13 /spl mu/m CMOS
Author :
Gu, Richard ; Lee, Wai
Author_Institution :
Texas Instrum., Dallas, TX
Abstract :
A 6.25 GHz PLL with an integrated LC-tank VCO designed and fabricated in 0.13 mum CMOS technology is described. For a deep submicron CMOS technology, leakage currents and limited voltage headroom degrade PLL performance. This paper introduces a new charge pump design with rail-to-rail operation and leakage cancellation techniques to overcome these constraints. Operated at 1 V supply voltage with an input reference clock frequency of 62.5 MHz, the PLL has 0.5 ps rms jitter at output frequency of 6.25 GHz
Keywords :
CMOS integrated circuits; jitter; phase locked loops; voltage-controlled oscillators; 0.13 micron; 0.5 ps; 1 V; 6.25 GHz; 62.5 MHz; CMOS technology; PLL; charge pump; input reference clock frequency; integrated LC-tank VCO; jitter; leakage cancellation; leakage currents; rail-to-rail operation; voltage headroom; CMOS technology; Charge pumps; Degradation; Frequency; Jitter; Leakage current; Phase locked loops; Rail to rail operation; Voltage; Voltage-controlled oscillators;
Conference_Titel :
Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
1-4244-0160-7
Electronic_ISBN :
1-4244-0161-5
DOI :
10.1109/ICSICT.2006.306373
