A 0.35 /spl mu/m CMOS 3-880 MHz PLL N/2 clock multiplier and distribution network with low jitter for microprocessors

The clock frequency for microprocessors can be de-coupled from external logic and memory speed when a phase-locked loop (PLL) clock frequency generator is integrated on chip to synthesize the higher internal clock frequency from a lower frequency external system clock, and improve I/O timing by eliminating (deskewing) delay through the on-chip clock distribution network. Microprocessor clock frequencies are increasing faster than process technology performance improvement by reducing the number of gates between latches. This increases the ratio of flipflops or latches to logic gates, and together with the fact that approximately twice the number of logic gates are used with each new architecture, leads to significant increase in clock capacitive load and power. This trend also drives up the delay in distributing and buffering the clock around the microprocessor to more than 50% of the clock cycle. This work identifies and minimizes major contributions to jitter and skew in the complete clock generator that consists of a PLL operating with the distribution network, for a 203mm/sup 2/ 300MHz microprocessor.