Digitally-controlled PLL with pulse width detection mechanism for error correction

This frequency synthesis PLL contains a pulse width detection (PWD) mechanism to measure and compare from cycle to cycle the width of up and down error pulses from a phase and frequency detector (PFD). Correction signals are sent to a digitally controlled oscillator (DCO) only if the phase error is small and increasing or large and not getting smaller. The advantages provided by the PWD and DCO are tolerance to process variations, ease of design and analysis, low bandwidth-to-operating frequency ratio (< 0.005), and deterministic error correction. An on-chip decoupling capacitor in the DCO (1OOpF) filters the supply and substrate noise to minimize jitter.