A monolithic wideband variable gain amplifier with a high gain range and low distortion

This variable-gain amplifier has architecture in which the linear input region is inversely proportional to the gain of the circuit. It incorporates a plurality of differential pairs (DP) coupled in parallel, forming a transadmittance stage. The input of each DP is provided with the input signal voltage, shifted by an offset voltage. The offset voltage of each individual DP is variable and independent of other DP offsets. When all offset voltages are equal, the transadmittance stage is set to maximum gain. The linear input region is then comparable to that of a single DP transadmittance stage. When the offset voltages are made equidistant at about 40 to 60 mV, the transadmittance stage is set to minimum gain. The linear input range is then increased compared to the situation of maximum gain and is dependent on the number of DPs. Gain settings between minimum and maximum gain are achieved by values of equidistance of the offset voltages between 0 and 40 to 60 mV. A prototype variable gain amplifier is in a 1 /spl mu/m triple metal bipolar process. It contains 32 parallel DPs and has a differential voltage input as well as output. The gain range is 0 to 25 dB. Active chip area is 0.15 mm/sup 2/. Supply voltage is 5 V and signal bandwidth is about 35 MHz at a power dissipation of 40 mW.