Title :
Symmetry Constraint for Analog Layout with CBL Representation
Author :
Liu, Jiayi ; Dong, Sheqin ; Chen, Fei ; Hong, Xianlong ; Ma, Yuchun ; Di Long
Author_Institution :
Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing
Abstract :
In the design of analog circuits, some pairs of devices are constrained to be placed symmetrically with respect to a common axis in order to cope with the device matching. In this paper, symmetry constraint is coped with CBL representation. In our algorithm, the incompleteness and redundancy of CBL can be corrected. And the experimental results show the effectiveness of our method
Keywords :
analogue circuits; circuit optimisation; integrated circuit layout; network topology; CBL representation; analog circuit layout; device matching; incompleteness; redundancy; symmetry constraint; Analog circuits; Binary trees; Circuit simulation; Computer science; Electronic design automation and methodology; Radio network; Research and development; Simulated annealing; Tree data structures; Voltage;
Conference_Titel :
Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
1-4244-0160-7
Electronic_ISBN :
1-4244-0161-5
DOI :
10.1109/ICSICT.2006.306418
