DocumentCode :
3472426
Title :
A 3.3 V 16 Mb nonvolatile virtual DRAM using a NAND flash memory technology
Author :
Tae-Sung Jung ; Do-Chan Choi ; Sung-Hee Cho ; Myong-Jae Kim ; Seung-Keun Lee ; Byung-Soon Choi ; Jin-Sun Yum ; San-Hong Kim ; Dong-Gi Lee ; Jong-Chang Son ; Myung-Sik Yong ; Heung-Kwun Oh ; Sung-Bu Jun ; Woung-Moo Lee ; Ejaz Haq ; Kang-Deog Suh ; Syed Ali
Author_Institution :
Samsung Electronics Co. Ltd., Kiheung, South Korea
fYear :
1997
fDate :
8-8 Feb. 1997
Firstpage :
398
Lastpage :
399
Abstract :
A 3.3V 16Mb nonvolatile memory has read and write operations fully DRAM-compatible except a longer RAS precharge time after write. Most systems with high-performance processors use a shadow nonvolatile memory uploaded to a fast DRAM to obtain zero wait-state performance. The introduced nonvolatile virtual DRAM (NVDRAM) eliminates the need for this redundancy, achieving high performance while reducing power consumption. Fast random access time (tRAC) with a NAND flash memory cell is achieved by using a folded bit-line architecture, and DRAM comparable column address access time (tkA) is achieved by sensing and latching 4k cells simultaneously.
Keywords :
DRAM chips; NAND circuits; memory architecture; 16 Mbit; 3.3 V; NAND flash memory technology; NVDRAM; RAS precharge time; column address access time; folded bit-line architecture; latching; nonvolatile virtual DRAM; power consumption; random access time; read operations; write operations; Decoding; Delay; Energy consumption; Latches; Nonvolatile memory; Paper technology; Random access memory; Read-write memory; Signal generators; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference, 1997. Digest of Technical Papers. 43rd ISSCC., 1997 IEEE International
Conference_Location :
San Francisco, CA, USA
ISSN :
0193-6530
Print_ISBN :
0-7803-3721-2
Type :
conf
DOI :
10.1109/ISSCC.1997.585457
Filename :
585457
Link To Document :
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