Title :
A 300 MHz dual port graphics RAM using port swap architecture
Author :
Nakase, Y. ; Mashiko, K. ; Tokuda, T.
Author_Institution :
System LSI Lab., Mitsubishi Electr. Corp., Itami, Japan
Abstract :
Graphics controllers are required to implement more functions such as 3D-RAM control and NTSC encoder. The color palette SRAM has been a great area eater in the controllers because of its dual port organization. Its memory cell size has been more than 50% larger than those of single port SRAMs. Single bit-line read/write architectures are effective for area reduction. However, there are problems of operation reliability or slow speed. The port swap architecture realizes a small memory cell size without the problems. The cell size is reduced more than 24%. The color palette with this architecture is fabricated in a 0.5 /spl mu/m CMOS process technology and operates up to 300 MHz. This speed is enough to support the practical highest resolution monitors in the world.
Keywords :
CMOS memory circuits; SRAM chips; colour graphics; computer graphic equipment; memory architecture; two-port networks; 0.5 micron; 300 MHz; 3D-RAM control; CMOS technology; NTSC encoder; color palette SRAM; dual port RAM; graphics controller; high resolution monitor; memory cell; port swap architecture; CMOS process; Clocks; Color; Control systems; Graphics; Large scale integration; Random access memory; Read-write memory; Switches; Timing;
Conference_Titel :
Solid-State Circuits Conference, 1997. Digest of Technical Papers. 43rd ISSCC., 1997 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-3721-2
DOI :
10.1109/ISSCC.1997.585458
