A 2 ns access, 285 MHz, two-port cache macro using double global bit-line pairs

High bandwidth has become one of the most important features in high-speed embedded cache memories in recent superscalar RISC processors. This 285 MHz, two-port 16kB (512/spl times/256) cache macro has a 2 ns access time. In this cache, the data of memory cells are sent to a read bus in the first half of the cycle time, and write data from a write bus are written to memory cells in the second half of the cycle time. This performance is achieved because of a hierarchical bit-line architecture that uses double global bit-line pairs (WGB), and a high-speed timing-free sense amplifier that shortens access time.