A 500 MHz 4 Mb CMOS pipeline-burst cache SRAM with point-to-point noise reduction coding I/O

A secondary cache SRAM is an indispensable CPU partner in a high-performance system. The main objectives are: 1) pipeline burst operation; 2) 32b 500MHz (2GB/s) I/Os, and 3) point-to-point communication with a CPU, as well as shortened latency and reduced noise and power caused by high-speed, high-bandwidth I/O operation. A pre-fetched pipeline scheme enables the cycle time for an internal memory core (I-cycle) to be extended by N times that of an external bus cycle (E-cycle). This is modified to an SRAM to achieve both 4b pipeline-burst cache operation and 500MHz I/O frequency. In this case, I-cycle time of 8ns is four times E-cycle time (2ns).