DocumentCode
3472595
Title
A 4.1 ns compact 54/spl times/54 b multiplier utilizing sign select Booth encoders
Author
Inoue, A. ; Ohe, R. ; Kashiwakura, S. ; Mitarai, S. ; Tsuru, T. ; Izawa, T. ; Goto, G.
Author_Institution
Fujitsu Labs. Ltd., Kawasaki, Japan
fYear
1997
fDate
8-8 Feb. 1997
Firstpage
416
Lastpage
417
Abstract
A sign select Booth encoder reduces transistor count of multipliers. This encoder is applied in a 54/spl times/54 b multiplier in 0.25 /spl mu/m CMOS technology. Because of the rapid progress in VLSI design technologies, consecutive improvements in operational speed and design integration are made. As a result of these improvements, interactive real-time 3D graphics applications have become available even in personal computers.
Keywords
CMOS digital integrated circuits; VLSI; encoding; floating point arithmetic; multiplying circuits; 0.25 micron; 4.1 ns; 54 bit; CMOS technology; VLSI design; high speed floating point computational core; interactive real-time 3D graphics; multiplier; personal computer; sign select Booth encoder; transistor count; Adders; Application software; Arithmetic; CMOS logic circuits; CMOS technology; Central Processing Unit; Graphics; Laboratories; Signal generators; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1997. Digest of Technical Papers. 43rd ISSCC., 1997 IEEE International
Conference_Location
San Francisco, CA, USA
ISSN
0193-6530
Print_ISBN
0-7803-3721-2
Type
conf
DOI
10.1109/ISSCC.1997.585465
Filename
585465
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