Title :
Proximity Inter-Chip Communication
Author :
Kuroda, Tadahiro
Author_Institution :
Keio Univ., Tokyo
Abstract :
A 1Tb/s 3W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1GHz and data rate of 1Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30mum. The total layout area is 2mm2 in 0.18mum CMOS and the chip thickness is 10mum. 4-phase TDMA reduces crosstalk and the BER is <10-12. Bi-phase modulation is used to improve noise immunity, reducing power in the transceiver
Keywords :
CMOS integrated circuits; high-speed integrated circuits; integrated circuit interconnections; time division multiple access; transceivers; 0.18 micron; 1 GHz; 1 Gbit/s; 10 micron; 3 W; CMOS process; bi-phase modulation; bit error rate; data transceivers; inter-chip transceiver; noise immunity; time division multiple access; Clocks; Crosstalk; Inductors; Large scale integration; Pulse generation; Time division multiple access; Transceivers; Transmitters; Virtual reality; Voltage;
Conference_Titel :
Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
1-4244-0160-7
Electronic_ISBN :
1-4244-0161-5
DOI :
10.1109/ICSICT.2006.306462
