• DocumentCode
    347271
  • Title

    Fast signature simulation for PPSFP simulators

  • Author

    Khadour, Firas ; Sun, Xiaoling

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Alberta Univ., Edmonton, Alta., Canada
  • fYear
    1999
  • fDate
    36465
  • Firstpage
    181
  • Lastpage
    189
  • Abstract
    This paper presents a novel technique to compute the signatures of multiple-input shift-registers (MISRs) in computer simulation when used in conjunction with parallel pattern single fault propagation (PPSFP) simulators. We first use a look-up table technique similar to compute a set of signatures, one for each input data stream of a MISR, at a common input tap position. Then we present an algorithm that modifies these signatures to reflect their actual input positions and obtain the final signature. Our experimental results show that the proposed signature simulation technique outperforms some existing methods with minimal memory requirements
  • Keywords
    VLSI; fault simulation; integrated circuit testing; logic simulation; logic testing; shift registers; table lookup; MISR; PPSFP simulators; computer simulation; fast signature simulation; lookup table technique; multiple-input shift-registers; parallel pattern single fault propagation simulators; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Computer simulation; Feedback; Logic circuits; Logic testing; Sun; Table lookup;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Defect and Fault Tolerance in VLSI Systems, 1999. DFT '99. International Symposium on
  • Conference_Location
    Albuquerque, NM
  • ISSN
    1550-5774
  • Print_ISBN
    0-7695-0325-x
  • Type

    conf

  • DOI
    10.1109/DFTVS.1999.802884
  • Filename
    802884