Time-shared modular redundancy for fault-tolerant FFT processors

Author

Piuri, Vincenzo ; Swartzlander, Earl E., Jr.

Author_Institution

Dept. Electron. & Inf., Politecnico di Milano, Italy

fYear

1999

fDate

36465

Firstpage

265

Lastpage

273

Abstract

This paper presents an efficient approach to concurrent error detection and correction for FFT processors by using time-shared modular redundancy. Digits of each input operand are partitioned in disjoint subsets: the nominal operations are performed more than once on each subset by using different arithmetic units. Comparison of results allows detection and, possibly, correction of errors. The modified architectures for detection and correction are analyzed and evaluated

Keywords

digital signal processing chips; error correction; error detection; fast Fourier transforms; fault tolerant computing; redundancy; arithmetic units; concurrent error correction; concurrent error detection; fault-tolerant FFT processors; input operand; modified architectures; nominal operations; time-shared modular redundancy; Complexity theory; Concurrent computing; Delay; Discrete Fourier transforms; Error correction; Fast Fourier transforms; Fault tolerance; Redundancy; Signal processing algorithms; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 1999. DFT '99. International Symposium on

Conference_Location

Albuquerque, NM

ISSN

1550-5774

Print_ISBN

0-7695-0325-x

Type

conf

DOI

10.1109/DFTVS.1999.802893

Filename

802893