Title :
Low Power Wide Dominos Design in sub-65nm CMOS Technologies
Author :
Wang, Jinhui ; Gong, Na ; Hou, Ligang ; Dong, Limin ; Wu, Wuchen
Author_Institution :
VLSI & Syst. Lab, Beijing Univ. of Technol.
Abstract :
Two novel low power wide OR domino designs are presented in this paper. With the same delay time, the two designed dominos decrease the active power by 8.92% to 17.25% and 13.79% to 25.84% as compared to the standard dual Vt dominos in a 45nm CMOS technology. In the meantime, the total leakage current is reduced significantly at two typical die temperatures
Keywords :
CMOS integrated circuits; delay circuits; integrated circuit design; leakage currents; low-power electronics; 45 nm; 65 nm; CMOS technologies; delay time; low power wide dominos design; total leakage current; CMOS technology; Circuits; Clocks; Delay effects; Energy consumption; Leakage current; MOS devices; Timing; Very large scale integration; Voltage;
Conference_Titel :
Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
1-4244-0160-7
Electronic_ISBN :
1-4244-0161-5
DOI :
10.1109/ICSICT.2006.306490
