Low Power High Speed Domino Logic based on Double Capacitive Body Biased Keeper

Author

Tung, H.-T. ; Son, J.-P. ; Kim, C.-R. ; Wang, N.-N. ; Kim, S.W.

Author_Institution

Dept. of Electr. & Comput. Eng., Korea Univ., Seoul

fYear

2006

fDate

23-26 Oct. 2006

Firstpage

1870

Lastpage

1872

Abstract

In this paper, a double capacitive body biased keeper (DCBBK) for domino logic gate is proposed. By using this technique, the threshold voltage of keeper transistor adapts to multi operating phase to reduce leakage power consumption and enhance speed compare to other techniques such as standard domino (SD) without body bias, dynamic body biased keeper (DBBK) and single capacitive body biased keeper (SCBBK). All the various body bias circuits are applied to a wide fan in OR domino gate for evaluating delay time, power consumption, power-delay product (PDP) and noise immunity. The simulation results for 0.18 mum Hynix CMOS technology show that DCBBK reduces 44%, 20%, 9% in power compare to SD, DBBK, SCBBK while DBBK, SCBBK, DCBBK improve 46% in speed than SD gate

Keywords

CMOS logic circuits; logic gates; low-power electronics; CMOS technology; OR domino gate; capacitive body biased keeper; domino logic gate; leakage power consumption; noise immunity; power-delay product; threshold voltage; CMOS logic circuits; CMOS technology; Circuit noise; Circuit simulation; Clocks; Delay effects; Energy consumption; Immune system; Phase noise; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on

Conference_Location

Shanghai

Print_ISBN

1-4244-0160-7

Electronic_ISBN

1-4244-0161-5

Type

conf

DOI

10.1109/ICSICT.2006.306492

Filename

4098566