Low Power Decimation Filter Design for GSM Sigma-Delta A/D Converter Application

A low power decimation filter design for GSM Sigma-Delta A/D converter application is proposed in this paper. The main power consumption CIC part is based on non-recursive structure that is an alternative to the standard CIC approach with a decimation factor of m-th power of two and m-th power of three. More research is done to find the break-even point of silicon area for non-recursive and recursive architecture of decimation filters with filter order 4. More than 70% of power can be saved for a filter with decimation factor 36 and filter order 4 by the non-recursive structure compared to the Hogenauer CIC architecture