A VLSI implementation of ECC combined with AES

Author

Wang, Jing ; Zeng, Xiaoyang ; Chen, Jun

Author_Institution

State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai

fYear

2006

fDate

2006

Firstpage

1899

Lastpage

1904

Abstract

This paper presents a new architecture to combine AES and ECC. The common calculation module between them is found after discussing algorithms of AES and ECC, and a novel improved multiplier is proposed. The performance of the crucial module is enhanced in two ways. One is adopting 8 parallel arithmetic cores in this work to reduce the complexity of the control part of the module and remove the extra RAM. The other is cutting down the data flow in circulation to make the data computed as compactly as it can afford. As a result, this implementation of ECC and AES is proved more efficient than others

Keywords

VLSI; cryptography; multiplying circuits; parallel processing; random-access storage; AES; DES; ECC; VLSI; advanced encrypt standard; data encryption standard; elliptic curve cryptography; parallel arithmetic cores; random access memory; Arithmetic; Coprocessors; Costs; Data security; Elliptic curve cryptography; Galois fields; Hardware; Information security; Laboratories; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on

Conference_Location

Shanghai

Print_ISBN

1-4244-0160-7

Electronic_ISBN

1-4244-0161-5

Type

conf

DOI

10.1109/ICSICT.2006.306501

Filename

4098575