An Embedded Processor for a Pairing-Based Cryptosystem

In recent times bilinear pairings have been instrumental in the design of many new cryptographic protocols and have provided elegant solutions to existing protocol problems. The eta pairing is one such pairing and is an efficient computation technique based on a generalization of the Duursma Lee method for calculating the Tate pairing. The pairing can be computed very efficiently on genus 2 hyperelliptic curves. In this paper it is demonstrated that this pairing operation is well suited to a dedicated parallel hardware implementation on an FPGA. An eta pairing processor is described in detail and the architectures required for such a system are discussed. Prototype implementation results are presented over a base field of F₂103 and the advantages of implementing the pairing on the dedicated processor are discussed