DocumentCode
3473042
Title
A High Performance and Low Power Hardware Architecture of Entropy Coder for H.264/AVC Baseline
Author
Lu, Wei-Jun ; Cao, Xi-Xin ; Yu, Dun-Shan ; Sheng, Shi-Min
Author_Institution
Dept. of Microelectron., Peking Univ., Beijing
fYear
2006
fDate
2006
Firstpage
1908
Lastpage
1910
Abstract
In this paper, the authors present a high performance and low power hardware architecture of entropy coder for H.264/AVC baseline. The authors implemented the architecture with SYNOPSYS design compiler and SMIC 0.13mum cell library. The result shows that the design need less area than the prior work and it can work at frequency 250Hz. In the worst case, it needs 1095 circles to code a macro block and can process 2306 QCIF (176times144) frames per second
Keywords
low-power electronics; video codecs; video coding; 0.13 micron; AVC coder; H.264 coder; QCIF; SYNOPSYS design compiler; entropy coder; hardware architecture; Automatic voltage control; Energy consumption; Entropy coding; Frequency; Hardware; Libraries; MPEG 4 Standard; Microelectronics; Video coding; Video compression;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on
Conference_Location
Shanghai
Print_ISBN
1-4244-0160-7
Electronic_ISBN
1-4244-0161-5
Type
conf
DOI
10.1109/ICSICT.2006.306503
Filename
4098577
Link To Document