Title :
A Compact Piplined Hardware Implementation of the AES-128 Cipher
Author :
Nedjah, Nadia ; Mourelle, Ld.M. ; Cardoso, Marco Paulo
Author_Institution :
Rio de Janeiro State Univ.
Abstract :
Advanced encryption standard - AES is the new encryption standard. In this paper, we propose a very efficient pipelined hardware implementation of AES-128 cipher. It has a competitive throughput of more than 2 Gbits per second. Besides, improving the encryption throughput, the pipeline can be taken advantage of if the number of rounds (currently 10) must increase for security reasons
Keywords :
cryptography; pipeline processing; 128 bit; AES-128 cipher; advanced encryption standard; compact pipelined hardware implementation; competitive encryption throughput; Computer architecture; Cryptography; Data security; Hardware; Pipelines; Polynomials; Processor scheduling; Throughput;
Conference_Titel :
Information Technology: New Generations, 2006. ITNG 2006. Third International Conference on
Conference_Location :
Las Vegas, NV
Print_ISBN :
0-7695-2497-4
DOI :
10.1109/ITNG.2006.1
