DocumentCode
3473090
Title
TranGen: a SAT-based ATPG for path-oriented transition faults
Author
Yang, Kai ; Cheng, Kwang-Ting ; Wang, Li.-C.
Author_Institution
Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
fYear
2004
fDate
27-30 Jan. 2004
Firstpage
92
Lastpage
97
Abstract
We present a SAT-based ATPG tool targeting on a path-oriented transition fault model. Under this fault model, a transition fault is detected through the longest sensitizable path. In the ATPG process, we utilize an efficient false-path pruning technique to identify the longest sensitizable path through each fault site. We demonstrate that our new SAT-based ATPG can be orders-of-magnitude faster than a commercial ATPG tool. To demonstrate the quality of the tests generated by our approach, we compare its resulting test set to three other test sets: a single-detection transition fault test set, a multiple-detection transition fault test set, and a traditional critical path test set added to the single-detection set. The superiority of our approach is demonstrated through various experiments based on statistical delay simulation and defect injection using benchmark circuits.
Keywords
automatic test pattern generation; circuit analysis computing; computability; fault diagnosis; SAT-based ATPG tool; benchmark circuits; false-path pruning technique; multiple-detection transition fault test set; path-oriented transition fault model; sensitizable path; single-detection transition fault test set; statistical delay simulation; Automatic test pattern generation; Benchmark testing; Circuit faults; Circuit simulation; Circuit testing; Delay; Electrical fault detection; Fault detection; Fault diagnosis; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2004. Proceedings of the ASP-DAC 2004. Asia and South Pacific
Print_ISBN
0-7803-8175-0
Type
conf
DOI
10.1109/ASPDAC.2004.1337546
Filename
1337546
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