A Novel Statistical Clock Skew Estimation Method

With the shrinking of IC feature size, clock skew uncertainty is introduced due to the presence of process variations. In order to accurately estimate the impact of process variations on clock-tree performance, clock skew has to be calculated statistically. We present a novel approach that is based on the truncation of a portion of circuit if the probability of some clock paths becoming the longest or shortest is small. Experimental results show that our method can effectively improve simulation speed with just a little of accuracy loss