Title :
Simplified AES Algorithm Resistant to Zero-Value Power Analysis and its VLSI Implementation
Author :
Zhao, Jia ; Zeng, Xiaoyang ; Han, Jun ; Chen, Jun
Author_Institution :
State-Key Lab. of ASIC & Syst., Fudan Univ., Shanghai
Abstract :
This paper proposes a simplified AES algorithm resistant to zero-value DPA (differential power analysis) attack and its VLSI implementation. This paper makes some improvements to the additive masking AES algorithm to decrease its complexity. Moreover, such methods as module reuse and calculation order alteration are used to reduce chip area while maintaining its speed. Using the HHNEC 0.25mum CMOS process, the scale of the design is about 43K equivalent gates and its system frequency is up to 40MHz. The throughputs of the 128-bit data encryption and decryption are as high as 470Mbit/s
Keywords :
CMOS integrated circuits; VLSI; cryptography; power integrated circuits; 0.25 micron; AES algorithm; CMOS process; HHNEC; VLSI implementation; data encryption; decryption; differential power analysis; zero value power analysis; Algorithm design and analysis; Application specific integrated circuits; CMOS process; Cryptography; Equations; Field programmable gate arrays; Frequency; Hardware; Throughput; Very large scale integration;
Conference_Titel :
Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
1-4244-0160-7
Electronic_ISBN :
1-4244-0161-5
DOI :
10.1109/ICSICT.2006.306534
