A Novel On-chip Debug System with Quick All-registers Scan Chain Based on JTAG

Author

Liu, Yang ; Wu, Wang-Hua ; Zhou, Xiao-Fang ; Zhou, Dian

Author_Institution

Dept. of Microelectron., Fudan Univ., Shanghai

fYear

2006

fDate

2006

Firstpage

1941

Lastpage

1943

Abstract

JTAG defines a serial interface to access test-dedicated logic embedded in integrated circuits. As an extension, a test platform based on JTAG standard can support general verifications and debug functions for SOC. The paper presents an on-chip debug system based on JTAG standard for embedded microprocessors. It provides powerful functions for the system. For example, hardware breakpoints, single step execution mode, monitoring the registers, programming. An all-registers structure is used to support quick all-registers monitoring functions. Moreover, the paper contributes to the research of no-gap transfer of debug functions

Keywords

boundary scan testing; embedded systems; integrated circuit testing; logic testing; microprocessor chips; JTAG standard; SOC; all-registers scan chain; all-registers structure; debug functions; embedded microprocessors; on-chip debug system; Circuit testing; Computer architecture; Control systems; Hardware; Integrated circuit testing; Logic testing; Microelectronics; Monitoring; Registers; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on

Conference_Location

Shanghai

Print_ISBN

1-4244-0160-7

Electronic_ISBN

1-4244-0161-5

Type

conf

DOI

10.1109/ICSICT.2006.306535

Filename

4098587