An integrated approach to timing-driven synthesis and placement of arithmetic circuits

In deep submicron (DSM) design, the interconnect delay becomes equally as or more important than that of logic gates. In particular, to achieve timing closure in DSM design, it is essential to consider the interconnect delay at an early stage of the synthesis process. Unfortunately, few successes of achieving a tight link of front-end synthesis to back-end layout have been reported, in a practical point of view, mainly due to the inaccuracy of predicting the layout effects during the synthesis. We address a new approach that refines the structure and placement of the circuit by iteratively performing the two tasks, timing-driven replacement and timing-driven resynthesis. The iterative mechanism of the two tasks practically tightly integrates the synthesis and placement tasks so that both of the effects of placement on the results of synthesis and the effects of synthesis on the results of placement are fully and effectively taken into account. From experiments using a set of benchmark designs, it is shown that the approach is quite effective, and efficient, producing designs with 6.6%-21.4% shorter timing over the conventional method.