DocumentCode
3473335
Title
NSGA-based parasitic-aware optimization of a 5GHz low-noise VCO
Author
Chu, Min ; Allsto, David J. ; Huard, Jeffrey M. ; Wong, Kim Y.
Author_Institution
Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
fYear
2004
fDate
27-30 Jan. 2004
Firstpage
169
Lastpage
174
Abstract
A parasitic-aware RF synthesis tool based on a nondominated sorting genetic algorithm (NSGA) is introduced. The NSGA-based optimizer casts the design problem as a multiobjective optimization problem and offers multiple solutions along the Pareto optimal front. Monte-Carlo simulations are then performed to efficiently assess sensitivity at solution points with respect to process, voltage, and temperature (PVT) variations. An example design of a 10 mW 5 GHz voltage-controlled oscillator (VCO) in 250 nm SiGe BiCMOS achieves a 12% tuning range with a phase noise of -133 dBc/Hz at 3 MHz offset. The figure-of-merit (FOM) is 188 dBc/Hz and power-frequency-tuning normalized FOM (PFTN-FOM) is -4dB.
Keywords
CMOS integrated circuits; Monte Carlo methods; Pareto optimisation; genetic algorithms; voltage-controlled oscillators; Monte-Carlo simulations; Pareto optimal front; VCO; multiobjective optimization problem; nondominated sorting genetic algorithm; parasitic-aware RF synthesis tool; power-frequency-tuning normalized figure-of-merit; voltage-controlled oscillator; Design optimization; Genetic algorithms; Germanium silicon alloys; Pareto optimization; Radio frequency; Silicon germanium; Sorting; Temperature sensors; Voltage; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2004. Proceedings of the ASP-DAC 2004. Asia and South Pacific
Print_ISBN
0-7803-8175-0
Type
conf
DOI
10.1109/ASPDAC.2004.1337560
Filename
1337560
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