DocumentCode
3473367
Title
A Double-Edge-Triggered Phase Frequency Detector for Low Jitter PLL
Author
Zhou, Yan-Ping ; Lu, Zhi-Qiang ; Ye, Yi-Zheng
Author_Institution
Microelectron. Center, Harbin Inst. of Technol.
fYear
2006
fDate
2006
Firstpage
1963
Lastpage
1965
Abstract
A double-edge-triggered phase frequency detector (dec-PFD) with modified true single phase clock D flop-flip (TSPC-DFF) is presented in a 0.35-mum CMOS technology. Due to a dead zone of 15 ps and three-state property, the dec-PFD can work up 1.5 GHz with decreased phase errors and jitter. The power consumed at 100 MHz is 0.74-mW from a 3.3-V power supply. The maximum frequency, phase characteristics and power consumption are simulated and compared with other phase frequency detectors (PFD´s)
Keywords
CMOS integrated circuits; flip-flops; jitter; phase detectors; phase locked loops; 0.35 micron; 0.74 mW; 100 MHz; 15 ps; 3.3 V; CMOS technology; double-edge-triggered phase frequency detector; low jitter PLL; phase locked loops; true single phase clock D flop-flip; CMOS technology; Clocks; Energy consumption; Jitter; Microelectronics; Phase detection; Phase frequency detector; Phase locked loops; Power supplies; Signal generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on
Conference_Location
Shanghai
Print_ISBN
1-4244-0160-7
Electronic_ISBN
1-4244-0161-5
Type
conf
DOI
10.1109/ICSICT.2006.306542
Filename
4098594
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