Title :
Design of a Hierarchy-Bus Based MPSoC on FPGA
Author :
Zhang, Wei ; Du, Gao-Ming ; Xu, Yi ; Gao, Ming-Lun ; Geng, Luo-Feng ; Zhang, Bing ; Jiang, Zhao-Yu ; Hou, Ning ; Tang, Yi-Hua
Author_Institution :
VLSI Res. Inst., Hefei Univ. of Technol.
Abstract :
The increasing system resources available on field-programmable gate arrays (FPGA) enable the integration of complex system on one programmable chip. This paper focuses on the design and implementation of a hierarchy-bus based multi-processor system-on-chip (MPSoC) integrating 4 ARM processors on FPGA. Experimental results had been obtained running at 60MHz with total area requiring 34% adaptive look-up tables (ALUTs) of Altera Stratix II EP2S180 and a maxim performance speedup of 3.2
Keywords :
field programmable gate arrays; microprocessor chips; system-on-chip; table lookup; ARM processors; FPGA; adaptive look-up tables; field-programmable gate arrays; hierarchy bus based MPSoC; hierarchy-bus based multiprocessor system-on-chip; programmable chip; Application software; Computer architecture; Costs; Digital signal processing; Field programmable gate arrays; Hardware; Integrated circuit interconnections; Master-slave; Operating systems; Very large scale integration;
Conference_Titel :
Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
1-4244-0160-7
Electronic_ISBN :
1-4244-0161-5
DOI :
10.1109/ICSICT.2006.306543
