Parasitic aware optimization of an RF power scavenging circuit with applications to Smartdust sensor networks

The small scale of Smartdust sensor networks poses unique challenges in the design and implementation of RF power scavenging systems. To meet these challenges, several design improvements to an RF power scavenging circuit integrated directly onto CMOS are presented. These improve RF to DC conversion efficiency through a reduction in the body effect and threshold voltage of diode connected MOSFETs and by reducing the sources of circuit parasitics that are unique to integrated circuits. Utilizing these improvements, a design goal of generating a 1V output voltage with a greater than 20% RF to DC conversion efficiency from RF energy levels measured in the environment (66 uW) was met. This represents better than double the RF to DC conversion efficiency of the conventional power matched RF energy harvesting circuit based on a Villard voltage doubler. The complete system, including matching circuitry is integrated directly onto a 130 nm CMOS process with no external passives and measures only 300 um by 600 um meeting the strict form factor requirement of Smartdust systems.