Design and Implementation of a 64/32-bit Floating-point Division, Reciprocal, Square root, and Inverse Square root Unit

Author

Shuang-yan, Chen ; Dong-hui, Wang ; Tie-jun, Zhang ; Chao-huan, Hou

Author_Institution

Inst. of Acoust., Chinese Acad. of Sci., Beijing

fYear

2006

fDate

2006

Firstpage

1976

Lastpage

1979

Abstract

This paper presents an efficient design and implementation of a configurable multifunctional floating-point unit for the computation of division, reciprocal, square root and inverse square root, which is fully compatible with the IEEE754 standard. Based on the Newton-Raphson method and utilizing fast parallel multipliers, the design is fast, scalable, easy to pipeline, and has very high precision. The design is implemented in Verilog, simulated in ModelSim, and then synthesized using synopsys design compiler with SMIC 0.18 micron standard cell library. Under worst condition, the critical path delay is 4.55ns

Keywords

Newton-Raphson method; floating point arithmetic; hardware description languages; multiplying circuits; 0.18 micron; 4.55 ns; IEEE754 standard; Newton-Raphson method; Verilog; floating-point division; inverse square root unit; multifunctional floating-point unit; parallel multipliers; synopsys design compiler; Acoustics; Chaos; Convergence; Costs; Delay; Floating-point arithmetic; Hardware; High performance computing; Pipelines; Signal processing algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on

Conference_Location

Shanghai

Print_ISBN

1-4244-0160-7

Electronic_ISBN

1-4244-0161-5

Type

conf

DOI

10.1109/ICSICT.2006.306546

Filename

4098598