Title :
Technology mapping and packing for coarse-grained, anti-fuse based FPGAs
Author :
Kang, Chang Woo ; Iranli, Ali ; Pedram, Massoud
Author_Institution :
Dept. of Electr. Eng. - Syst., Univ. of Southern California, Los Angeles, CA, USA
Abstract :
We present a new synthesis flow for antifuse based FPGAs with multiple-output logic cells. The flow consists of two steps: mapping and packing. The mapper finds mapping solutions using a dynamic programming-based approach that finds the best match at each node of the decomposed target circuit. After this mapping step is completed, the resulting netlist of cells is optimally packed into net list of logic cells by using a multidimensional coin change problem formulation which is again solved by a dynamic programming based approach. Experimental results for Quicklogic´s pASIC3 logic family are provided to assess the effectiveness of the proposed mapping and packing techniques.
Keywords :
application specific integrated circuits; dynamic programming; field programmable gate arrays; logic CAD; Quicklogic pASIC3 logic family; antifuse based FPGA; dynamic programming-based approach; logic cell packing; multidimensional coin change problem formulation; multiple-output logic cells; technology mapping; Application specific integrated circuits; Circuit testing; Consumer electronics; Field programmable gate arrays; Libraries; Logic circuits; Logic programming; Multiplexing; Programmable logic arrays; Reconfigurable logic;
Conference_Titel :
Design Automation Conference, 2004. Proceedings of the ASP-DAC 2004. Asia and South Pacific
Print_ISBN :
0-7803-8175-0
DOI :
10.1109/ASPDAC.2004.1337567
