• DocumentCode
    347347
  • Title

    On avoiding undetectable faults during test generation

  • Author

    Pomeranz, Irith ; Reddy, Sudhakar M.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
  • fYear
    1999
  • fDate
    25-28 May 1999
  • Firstpage
    90
  • Lastpage
    95
  • Abstract
    We use a property that distinguishes most of the undetectable faults in a circuit from detectable ones, in order to avoid targeting undetectable faults during test generation. We show that it is possible to avoid most of the undetectable faults until most of the detectable faults are detected. The test generation process is speeded-up by avoiding undetectable faults, since wasted effort expended in trying to detect undetectable faults is avoided. When all or most of the faults that remain undetected by the test generator appear to be undetectable faults, a procedure for identifying undetectable faults may be used. Detectable faults, if any such faults remain, may then be given to the test generator to obtain complete fault coverage. We study the proposed property in conjunction with test generation processes for both combinational and sequential circuits.
  • Keywords
    fault diagnosis; logic testing; combinational circuits; complete fault coverage; logic testing; redundancy; sequential circuits; test generation; undetectable faults; Circuit faults; Circuit simulation; Circuit testing; Cities and towns; Computational modeling; Electrical fault detection; Fault detection; Fault diagnosis; Sequential analysis; Sequential circuits;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    European Test Workshop 1999. Proceedings
  • Conference_Location
    Constance, Germany
  • Print_ISBN
    0-7695-0390-X
  • Type

    conf

  • DOI
    10.1109/ETW.1999.804292
  • Filename
    804292