Title :
Test data compression technique using selective don´t-care identification
Author :
Hayashi, Terumine ; Yoshioka, Haruna ; Shinogi, Tsuyoshi ; Kita, Hajime ; Takase, Haruhiko
Author_Institution :
Dept. of Electr. & Electron. Eng., Mie Univ., Tsu, Japan
Abstract :
We propose an effective method for reducing test data volume under multiple scan chain designs. The proposed method is based on (1) reduction of distinct scan vectors (words) using selective don´t-care identification, and (2) reduction of total test data volume using single/double length coding. In (1), don´t-care identification is repeatedly applied under conditions that each bit in specified scan vectors is fixed to binary value (0 or 1). In (2), the code length for frequent scan vectors is shortened in the manner that the code length for rare scan vectors is designed as double of that for frequent ones. The proposed method achieves not only high compression efficiency, but also has a feature that the decompressor circuits are rather simple like combinational ones. The effectiveness of the proposed method is shown through experiments for ISCAS´89 and ITC´99 benchmark circuits.
Keywords :
circuit CAD; combinational circuits; data compression; logic CAD; benchmark circuits; multiple scan chain designs; scan vectors; selective don´t-care identification; single length coding; test data compression technique; Benchmark testing; Circuit testing; Compaction; Costs; Data engineering; Design engineering; Energy consumption; Large scale integration; Test data compression; Time of arrival estimation;
Conference_Titel :
Design Automation Conference, 2004. Proceedings of the ASP-DAC 2004. Asia and South Pacific
Print_ISBN :
0-7803-8175-0
DOI :
10.1109/ASPDAC.2004.1337571