Title :
A High-Speed Area-Efficient Architecture for the Arithmetic in GF(2m)
Author :
Wang, Jian ; Jiang, Anping
Author_Institution :
Dept. of Microelectron., Peking Univ., Beijing
Abstract :
Finite fields have been used for numerous applications including error-control coding and cryptography. This paper presents a high-speed area-efficient architecture for arithmetic that can support arbitrary irreducible polynomials in GF(2m). The arithmetic unit can perform the Galois field arithmetic operations of addition, subtraction, multiplication, squaring, inversion and division. The least significant bit first (LSB-first) scheme for modular multiplication and the extended Euclid´s algorithm for modular inversion are both modified for the arithmetic unit. The architecture has been implemented using 0.18-mum CMOS standard cell library, the clock frequency can reach 300MHz for a 512-bit arithmetic unit. The gate count of the circuit is only 48528
Keywords :
CMOS digital integrated circuits; Galois fields; cryptography; digital arithmetic; encoding; error correction codes; 0.18 micron; 300 MHz; 512 bit; CMOS standard cell library; GF(2m); Galois field arithmetic operations; addition; arithmetic unit; cryptography; division; error-control coding; extended Euclid algorithm; finite fields; inversion; irreducible polynomials; least significant bit first; multiplication; squaring; subtraction; Arithmetic; Circuits; Clocks; Cryptography; Frequency; Galois fields; Hardware; Libraries; Microelectronics; Polynomials;
Conference_Titel :
Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
1-4244-0160-7
Electronic_ISBN :
1-4244-0161-5
DOI :
10.1109/ICSICT.2006.306579
