Title :
Design of the Fast Acquisition PLL with Wide Tuning Range
Author :
Ge, Yan ; Jia, Song ; Ji, Lijiu
Author_Institution :
Inst. of Microelectron., Peking Univ., Beijing
Abstract :
In this paper we present a design of adaptive gain phase-locked loop (PLL) which features fast acquisition, low jitter and wide tuning range. A dual-edge-triggered phase frequency detector (PFD) and a self-regulated voltage controlled oscillator (VCO) are employed in this design to realize the aforementioned properties. The measured results show that the experimental chip with a standard logic 0.5-mum 5V CMOS process has the acquisition time less than 150ns @ 37% frequency variation and output rms jitter of 23ps @ 640MHz
Keywords :
phase locked loops; voltage-controlled oscillators; 0.5 micron; 5 V; 640 MHz; CMOS process; PLL; VCO; adaptive gain phase-locked loop; dual-edge-triggered phase frequency detector; voltage controlled oscillator; wide tuning range; CMOS logic circuits; Frequency measurement; Jitter; Measurement standards; Phase frequency detector; Phase locked loops; Semiconductor device measurement; Time measurement; Tuning; Voltage-controlled oscillators;
Conference_Titel :
Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
1-4244-0160-7
Electronic_ISBN :
1-4244-0161-5
DOI :
10.1109/ICSICT.2006.306584
