DocumentCode :
3473861
Title :
Design and Verification for VAC SOC in Mixed DFT Frame
Author :
Zhang, Jin-yi ; Zhou, Jun ; Xiong, Yan-Shuang ; Han, Tong-Hui
Author_Institution :
Microelectron. R&D Center, Shanghai Univ.
fYear :
2006
fDate :
23-26 Oct. 2006
Firstpage :
2043
Lastpage :
2045
Abstract :
A totally new mixed DFT frame (MDF) is introduced in this thesis which adapts for VAC SOC. VAC SOC consists of IPs with different circuit structure. Through the test pattern simulation and fault coverage evaluation, MDF is proved to be an efficient DFT frame that can obtain extremely high fault coverage under limited testing cost, and moreover, MDF is very popular and practical
Keywords :
automatic test pattern generation; design for testability; fault simulation; system-on-chip; DFT frame; VAC SOC; design for testability; fault coverage evaluation; system-on-chip; test pattern simulation; Circuit faults; Circuit testing; Communication standards; Control systems; Costs; Design for testability; Logic circuits; Microelectronics; Power capacitors; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
1-4244-0160-7
Electronic_ISBN :
1-4244-0161-5
Type :
conf
DOI :
10.1109/ICSICT.2006.306588
Filename :
4098619
Link To Document :
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