DocumentCode
3473928
Title
A Novel Low Leakage Power FPGAs Look-Up Table
Author
Yang, Song ; Wang, Hong ; Yang, Zhi-jia ; Yan, Yong-zhi
Author_Institution
Shenyang Inst. of Autom., Chinese Acad. of Sci., Shenyang
fYear
2006
fDate
23-26 Oct. 2006
Firstpage
2052
Lastpage
2054
Abstract
This paper proposed a novel low leakage FPGAs look-up table (LUT) that can operate in three different modes: high-speed, low-power or sleep. In high-speed mode, the LUT provide similar power and performance to a conventional LUT. In low-power mode, as the expense of speed, leakage power is reduced by 68%~73% vs. high-speed mode. Leakage power in sleep mode is over 95% lower than in high-speed mode
Keywords
field programmable gate arrays; table lookup; field programmable gate array; look-up table; low leakage power FPGA; Circuits; Diodes; Energy consumption; Field programmable gate arrays; Flip-flops; Programmable logic arrays; Subthreshold current; Switches; Table lookup; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on
Conference_Location
Shanghai
Print_ISBN
1-4244-0160-7
Electronic_ISBN
1-4244-0161-5
Type
conf
DOI
10.1109/ICSICT.2006.306591
Filename
4098622
Link To Document