A Partial Parallel folding Multiplier Design for 1024 bit Modular Multiplication

A 1056 times 32 bit partial parallel folding multiplier for security chip based on 0.25mum CMOS technology is proposed in this paper, of 200MHz working frequency. The multiplier is composed of two 572 times 32 bit partial parallel multipliers with reconfigurable data path between them, and this folding architecture can be divided in two for 544 times 544 bit multiplication. The core component of multiplier is the 4-2 and 6-2 compressors array, it can compress 16 bit products and carry-ins with the same weight into 1 bit sum and carry a cycle. So we shortened the critical path on it by optimizing its internal XOR and carry generator circuits as well as layouts. In the worst case simulation, the delay of the block is less than 3.4ns. And the simulation of the entire multiplier indicates that a 1056 times 1056 bit multiplication can be calculated out in 70 cycles