Title :
Cubic Packing with Various Candidates for 3D IC Design
Author :
Ma, Yuchun ; Zhuoyuan Li ; Hong, Xianlong ; Cong, Jason ; Dong, Sheqin
Author_Institution :
Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beiijng
Abstract :
In this paper, we introduce various candidates for circuit blocks so that the floorplanner can dynamically choose the implementations of blocks to optimize the whole chip. Especially in 3D IC design, some components may occupy more than one layer, we propose a novel method to optimize the cubic packing with various candidates. Based on 3D-CBL (3-dimensional corner block list) representation, we can handle the layer number constraints heuristically and we guarantee the feasibility of the final results. Experimental results show that our algorithm is effective and efficient
Keywords :
VLSI; integrated circuit layout; 3D corner block list representation; 3D integrated circuit design; cubic packing; floorplanner; layer number constraints; Computer science; Constraint optimization; Delay; Design optimization; Optimization methods; Silicon; Three-dimensional integrated circuits; Upper bound; Very large scale integration; Wire;
Conference_Titel :
Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
1-4244-0160-7
Electronic_ISBN :
1-4244-0161-5
DOI :
10.1109/ICSICT.2006.306622
