Title :
Modeling of coplanar waveguide for buffered clock tree
Author :
Chen, Jun ; He, Lei
Author_Institution :
Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
Abstract :
Owing to inductive effect, coplanar waveguide (CPW) is widely used to achieve signal integrity in high performance clock designs. We first propose a piece-wise linear (PWL) model for the far-end response of a CPW considering ramp input and capacitive loading. The PWL model has a high accuracy but uses at least l000x less time compared to SPICE. We then apply the PWL model to synthesize the CPW geometry for clock trees considering constrains of rising time and oscillation at sinks. We obtain a spectrum of solutions with smooth tradeoff between area and power.
Keywords :
RLC circuits; buffer circuits; coplanar waveguides; network topology; piecewise linear techniques; buffered clock tree synthesis; capacitive loading; coplanar waveguide; high performance clock design; inductive effect; piece-wise linear model; ramp input; signal integrity; Clocks; Computational modeling; Coplanar waveguides; Delay; Geometry; Piecewise linear techniques; Power transmission lines; SPICE; Signal synthesis; Solid modeling;
Conference_Titel :
Design Automation Conference, 2004. Proceedings of the ASP-DAC 2004. Asia and South Pacific
Print_ISBN :
0-7803-8175-0
DOI :
10.1109/ASPDAC.2004.1337601
