A Novel Frequency Constrained Floorplanning Algorithm

Interconnect effects have become a more and more important factor in high performance chip design. In traditional floorplanners, the lack of information about high level synthesis (HLS) timing based on cycle paths often leads to frequency violation in flooplan. In this paper, timing analysis including interconnect delay and chip frequency optimization are introduced to floorplanning, which brings synchronous circuit optimization on logic structure and physical design. Experimental results show that optimized designs can not only satisfy and optimize chip frequency constraint but also obtained a good packing with minimized area