DocumentCode :
3474282
Title :
LPRAM: a low power DRAM with testability
Author :
Bhattacharjee, Subhasis ; Pradhan, Dhiraj K.
Author_Institution :
Bristol Univ., UK
fYear :
2004
fDate :
27-30 Jan. 2004
Firstpage :
390
Lastpage :
393
Abstract :
To date all the proposal for low power designs of RAMs essentially focus on circuit level solutions. What we propose here is a novel architecture level solution. Our methodology provides a systematic trade off between power and area. Also, it allows tradeoff between test time and power consumed in test mode. Significantly, too, the proposed design has the potential to achieve performance improvements while reducing power. In this respect it stands apart from other approaches where the conventional wisdom of reducing power reduces speed.
Keywords :
DRAM chips; VLSI; integrated circuit testing; low-power electronics; LPRAM; circuit level solution; low-power DRAM; Capacitance; Circuit testing; DH-HEMTs; Decoding; Frequency; Power dissipation; Proposals; Random access memory; Read-write memory; Threshold voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2004. Proceedings of the ASP-DAC 2004. Asia and South Pacific
Print_ISBN :
0-7803-8175-0
Type :
conf
DOI :
10.1109/ASPDAC.2004.1337606
Filename :
1337606
Link To Document :
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