A simple thermal-balance model for floorplanning based b/sup *-trees

The thermal problem has been emerged as one of the key issues for next-generation IC design. In this paper, we propose a floorplanning tool that aims at reducing hot spots while optimizes design metrics such as area and total wire length. The simulated annealing was employed in our algorithm. The experimental results using MCNC benchmarks show that the thermal distributed evenly and the temperature of the "hot spots" decreased greatly in the chip, while providing floorplan that are as compact as the traditional area-oriented techniques