Interconnect design methods for memory design

We present a solution to the problem of designing interconnects for memory devices. More precisely, it solves the automatic routing problem of memory peripheral circuits as an over-the-cell channel routing problem under prespecified routing topologies and performance constraints. The proposed routing method, named TANAR, consists of two steps: a performance-driven net partitioning step, which constructs a routing topology for each net according to performance constraints, and a performance-driven track assignment step, which reduces the crosstalk noise. Experimental results demonstrate that TANAR significantly reduces both crosstalk for noise sensitive nets, and delay for timing critical nets while minimizing channel height.