DocumentCode :
3474460
Title :
Design methodology for IRA codes
Author :
Kienle, Frank ; Wehn, Norbert
Author_Institution :
Microelectron. Syst. Design Res. Group, Kaiserslautern Univ., Germany
fYear :
2004
fDate :
27-30 Jan. 2004
Firstpage :
459
Lastpage :
462
Abstract :
Channel coding is an important building block in communication systems since it ensures the quality of service. Irregular repeat-accumulate (IRA) codes belong to the class of low-density parity-check (LDPC) codes and even outperform the recently introduced turbo-codes of current communication standards. IRA codes can be represented by a Tanner graph with arbitrary connections between nodes of given degrees. The implementation complexity of an IRA decoders is dominated by the randomness of these connections. We present for the first time an IRA decoder architecture which can process any given IRA code. We developed a joint graph-decoder design methodology to construct the Tanner graph of a given IRA code which can be efficiently processed by this decoder architecture without any RAM access conflicts. We show that these constructed IRA codes can outperform the UMTS turbo-codes.
Keywords :
channel coding; decoding; graph theory; parity check codes; telecommunication standards; turbo codes; IRA code; IRA decoder; Tanner graph; channel coding; communication standard; communication system; graph-decoder design; low-density parity-check code; quality of service; repeat-accumulate code; turbo-code; Channel coding; Communication standards; Decoding; Design methodology; Hardware; Microelectronics; Parallel architectures; Parity check codes; Quality of service; Turbo codes;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2004. Proceedings of the ASP-DAC 2004. Asia and South Pacific
Print_ISBN :
0-7803-8175-0
Type :
conf
DOI :
10.1109/ASPDAC.2004.1337619
Filename :
1337619
Link To Document :
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