Title :
A Wide-Band Digital Phase-Locked Looop
Author :
Ambarish, Shilpa ; Wagdy, Mahmoud Fawzy
Author_Institution :
California State University, Long Beach
Abstract :
A high speed digital phase-locked loop (DPLL) is designed using 0.18..m CMOS process, using a 3.3V power supply. It operates in the frequency range 55MHz — 1.43GHz. A (PFD) phase frequency detector has a zero dead-zone by including delay elements in the Reset path. The current source used in the charge pump makes it insensitive to supply variations and provides ripple-free control voltage for the VCO (voltage controlled oscillator), which provides low jitter and no overshoot in locking transients. A high damping factor of 1.65 is used to keep the PLL stable. Simulation results using CADENCE tools are provided to verify the desired performance.
Keywords :
CMOS process; Charge pumps; Delay; Jitter; Phase frequency detector; Phase locked loops; Power supplies; Voltage control; Voltage-controlled oscillators; Wideband;
Conference_Titel :
Information Technology: New Generations, 2006. ITNG 2006. Third International Conference on
Print_ISBN :
0-7695-2497-4
DOI :
10.1109/ITNG.2006.21
