Title :
A New Solution to Implement Multi-Full-Scan-Chain Test with JTAG
Author :
Wang, Xin-Xin ; Liang, Li-Ping ; Wang, Xing-Jun
Author_Institution :
Res. Inst. of Inf. Technol., Tsinghua Univ., Beijing
Abstract :
This paper presents a DFT (design for test) solution which combines boundary-scan and full-scan together in SoC testability design. Using this method, full scan test and boundary scan test can be easily performed just through the common IEEE 1149.1 (JTAG) access interface. Our final goal is not only to implement fewer test-pin-count, but rather to provide an IEEE 1149.1 compatible architecture to achieve the unified boundary scan test and multi-full-scan-chain test. To do this, a new instruction "SCAN" is added in JTAG instruction register, at the same time, a few kinds of modified boundary scan cells and minor modifications to the TAP controller are adopted
Keywords :
IEEE standards; boundary scan testing; design for testability; integrated circuit testing; system-on-chip; IEEE 1149.1 access interface; JTAG instruction register; SoC testability design; TAP controller modification; boundary scan test; design for testing; full scan test; multi-full-scan-chain test; test-pin-count; Circuit testing; Communication standards; Costs; Design for testability; Electronics industry; Frequency synchronization; Information technology; Performance evaluation; Pins; Semiconductor device testing;
Conference_Titel :
Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
1-4244-0160-7
Electronic_ISBN :
1-4244-0161-5
DOI :
10.1109/ICSICT.2006.306667
