DocumentCode :
3474636
Title :
DEPOGIT: dense power-ground interconnect architecture for physical design integrity
Author :
Kurokawa, Atsushi ; Ono, Nobuto ; Kage, T. ; Masuda, Hiroji
fYear :
2004
fDate :
27-30 Jan. 2004
Firstpage :
517
Lastpage :
522
Abstract :
In recent deep submicron VLSI design, signal integrity (SI) and power-ground integrity (PGI) have become very important to design in a short time. As a solution, we propose DEPOGIT, which is a new dense power-ground interconnect architecture that realizes more robust physical design integrity. This architecture is a method of running both the power and ground wires adjacent to the signal wires. This provides not only the general shielding effect but also explicit decoupling capacitance (decap) by means of the wires. Using this architecture also guarantees regularity, thus reducing manufacturing variations in interconnects. As a result of quantitative analysis performed using 90 nm technology node, we demonstrate that high-quality decap of over 50 nF in a 10 mm square chip can be obtained, the resistive IR-drop can be less than 20% of that of a conventional power grid, transient peak noise can be reduced by about 80%, and the inductive crosstalk effect of the signal wire can be greatly reduced.
Keywords :
VLSI; circuit layout CAD; interconnections; power electronics; system-on-chip; DEPOGIT; crosstalk effect; decoupling capacitance; dense power-ground interconnect architecture; physical design integrity; power-ground integrity; quantitative analysis; resistive IR-drop; signal wire; submicron VLSI design; Capacitance; Crosstalk; Manufacturing; Pareto analysis; Performance analysis; Robustness; Signal analysis; Signal design; Very large scale integration; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2004. Proceedings of the ASP-DAC 2004. Asia and South Pacific
Print_ISBN :
0-7803-8175-0
Type :
conf
DOI :
10.1109/ASPDAC.2004.1337629
Filename :
1337629
Link To Document :
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