DocumentCode
3474695
Title
A sub-mW MPEG-4 motion estimation processor core for mobile video application
Author
Kuroda, Y. ; Miyakoshi, J. ; Miyama, M. ; Imamura, K. ; Hashimoto, H. ; Yoshimoto, M.
Author_Institution
Fac. of Eng., Kanazawa Univ., Japan
fYear
2004
fDate
27-30 Jan. 2004
Firstpage
527
Lastpage
528
Abstract
We describe a sub-mW motion estimation processor core for MPEG-4 video encoding. It features a gradient descent search algorithm whose computation power is only 7% of the conventional l:4-subsampling search, producing higher picture quality. Another feature is an optimized SIMD datapath architecture to decrease a clock frequency and an operating voltage. It has been fabricated with CMOS 5-metal 0.18 μm technology. The measured power consumption to process a QCIF15 fps video is 0.4 mW under 0.85 MHz@1.0 V.
Keywords
CMOS integrated circuits; mobile computing; motion estimation; parallel processing; power consumption; video coding; CMOS technology; MPEG-4 motion estimation processor core; clock frequency; gradient descent search algorithm; mobile video application; optimized SIMD datapath architecture; picture quality; CMOS technology; Clocks; Computer architecture; Encoding; Energy consumption; Frequency; MPEG 4 Standard; Motion estimation; Power measurement; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2004. Proceedings of the ASP-DAC 2004. Asia and South Pacific
Print_ISBN
0-7803-8175-0
Type
conf
DOI
10.1109/ASPDAC.2004.1337632
Filename
1337632
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